YING, Wang; YUN, Han; XINYU, Xu. Joint Optimization of Data Path and Memory Hierarchy for Deep Learning Accelerator Architectures. International Academic Journal of Engineering and Technology Science, [S. l.], v. 2, p. 13–18, 2026. Disponível em: https://h-tsp.com/index.php/iajeet/article/view/270. Acesso em: 17 apr. 2026.